I. Field of the Disclosure
The technology of the disclosure relates generally to arbitration of bus transactions on a communications bus in a processor-based system and power management of a communications bus.
II. Background
Modern digital systems and processor-based designs typically employ a communications bus. The communications bus is configured to facilitate devices or peripherals, acting as master devices, sending communications to receiving peripherals or devices, acting as slave devices. For example, if a master device desires to send a read request to a slave device, the master device provides control information that includes an address and read command on the communications bus. The communications bus directs the command to the appropriate slave device coupled to the communications bus according to the control information. Further, master and slave devices coupled to the communications bus may be provided along with a communications bus on a single chip to provide a system-on-a-chip (SOC). SOCs are particularly useful in portable electronic devices because of their integration of multiple subsystems that can provide multiple features and applications in a single chip.
An arbiter can be provided for the communications bus to direct or arbitrate bus transactions from master devices to slave devices coupled to the communications bus. Bus arbitration may, for example, prevent bus transaction collisions. For example, a system that includes a computer processing unit (CPU), a digital signal processor (DSP), and direct memory access (DMA) controller coupled to a communications bus may all have access to a shared memory system also coupled to the communications bus. The arbiter arbitrates memory access requests from these devices to the shared memory system so that bus resources are allocated between competing requests from master devices. However, it is desired that the arbiter be configured not to expend routing resources processing requests from one master device on the communications bus that will cause an unacceptable increase in latencies of other requests by other master devices.